Collaboration diagram for ARMv7-M Specific Implementation:

Detailed Description

ARMv7-M specific port code, structures and macros.

Data Structures
struct	context
	Platform dependent part of the `Thread` structure. More...
Functions
	CH_IRQ_HANDLER (SysTickVector)
	System Timer vector.
void	SVCallVector (void)
	SVC vector.
void	PendSVVector (void)
	PendSV vector.
void	_port_init (void)
	Port-related initialization code.
void	_port_irq_epilogue (void)
	Exception exit redirection to _port_switch_from_isr().
void	_port_switch_from_isr (void)
	Post-IRQ switch code.
void	_port_switch (Thread ntp, Thread otp)
	Performs a context switch between two threads.
void	_port_thread_start (void)
	Start a thread by invoking its work function.
void	port_halt (void)
	Halts the system.
Defines
#define	CORTEX_BASEPRI_DISABLED 0
	Disabled value for BASEPRI register.
#define	PORT_IDLE_THREAD_STACK_SIZE 16
	Stack size for the system idle thread.
#define	PORT_INT_REQUIRED_STACK 32
	Per-thread stack overhead for interrupts servicing.
#define	CORTEX_ENABLE_WFI_IDLE FALSE
	Enables the use of the WFI instruction in the idle thread loop.
#define	CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
	SYSTICK handler priority.
#define	CORTEX_USE_FPU CORTEX_HAS_FPU
	FPU support in context switch.
#define	CORTEX_SIMPLIFIED_PRIORITY FALSE
	Simplified priority handling flag.
#define	CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
	SVCALL handler priority.
#define	CORTEX_VTOR_INIT 0x00000000
	NVIC VTOR initialization expression.
#define	CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
	NVIC PRIGROUP initialization expression.
#define	CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
	Maximum usable priority for normal ISRs.
#define	CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY)
	BASEPRI level within kernel lock.
#define	CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
	PendSV priority level.
#define	CH_ARCHITECTURE_ARM_v7M
	Macro defining the specific ARM architecture.
#define	CH_ARCHITECTURE_NAME "ARMv7-M"
	Name of the implemented architecture.
#define	CH_CORE_VARIANT_NAME "Cortex-M3"
	Name of the architecture variant.
#define	CH_PORT_INFO "Advanced kernel mode"
	Port-specific information string.
#define	SETUP_CONTEXT(workspace, wsize, pf, arg)
	Platform dependent part of the `chThdCreateI()` API.
#define	STACK_ALIGN(n) ((((n) - 1) \| (sizeof(stkalign_t) - 1)) + 1)
	Enforces a correct alignment for a stack area size value.
#define	THD_WA_SIZE(n)
	Computes the thread working area global size.
#define	WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
	Static working area allocation.
#define	PORT_IRQ_PROLOGUE()
	IRQ prologue code.
#define	PORT_IRQ_EPILOGUE() _port_irq_epilogue()
	IRQ epilogue code.
#define	PORT_IRQ_HANDLER(id) void id(void)
	IRQ handler function declaration.
#define	PORT_FAST_IRQ_HANDLER(id) void id(void)
	Fast IRQ handler function declaration.
#define	port_init() _port_init()
	Port-related initialization code.
#define	port_lock()
	Kernel-lock action.
#define	port_unlock()
	Kernel-unlock action.
#define	port_lock_from_isr() port_lock()
	Kernel-lock action from an interrupt handler.
#define	port_unlock_from_isr() port_unlock()
	Kernel-unlock action from an interrupt handler.
#define	port_disable() asm volatile ("cpsid i" : : : "memory")
	Disables all the interrupt sources.
#define	port_suspend()
	Disables the interrupt sources below kernel-level priority.
#define	port_enable()
	Enables all the interrupt sources.
#define	port_wait_for_interrupt()
	Enters an architecture-dependent IRQ-waiting mode.
#define	port_switch(ntp, otp) _port_switch(ntp, otp)
	Performs a context switch between two threads.
Typedefs
typedef void *	regarm_t
	Generic ARM register.

Function Documentation

CH_IRQ_HANDLER ( SysTickVector )

System Timer vector.

This interrupt is used as system tick.

Note:: The timer must be initialized in the startup code.

Definition at line 40 of file chcore_v7m.c.

References CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, chSysLockFromIsr, chSysTimerHandlerI(), and chSysUnlockFromIsr.

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void SVCallVector ( void )

SVC vector.

The SVC vector is used for exception mode re-entering after a context switch.

Note:: The PendSV vector is only used in advanced kernel mode.

Definition at line 58 of file chcore_v7m.c.

References port_unlock_from_isr.

void PendSVVector ( void )

PendSV vector.

The PendSV vector is used for exception mode re-entering after a context switch.

Note:: The PendSV vector is only used in compact kernel mode.

Definition at line 85 of file chcore_v7m.c.

void _port_init ( void )

Port-related initialization code.

Definition at line 111 of file chcore_v7m.c.

References CORTEX_PRIGROUP_INIT, CORTEX_PRIORITY_MASK, CORTEX_PRIORITY_PENDSV, CORTEX_PRIORITY_SVCALL, CORTEX_PRIORITY_SYSTICK, CORTEX_VTOR_INIT, HANDLER_PENDSV, HANDLER_SVCALL, HANDLER_SYSTICK, and nvicSetSystemHandlerPriority().

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void _port_irq_epilogue ( void )

Exception exit redirection to _port_switch_from_isr().

Definition at line 141 of file chcore_v7m.c.

References _port_switch_from_isr(), chSchIsPreemptionRequired(), port_lock_from_isr, and port_unlock_from_isr.

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void _port_switch_from_isr ( void )

Post-IRQ switch code.

Exception handlers return here for context switching.

Definition at line 200 of file chcore_v7m.c.

References chSchDoReschedule(), dbg_check_lock(), dbg_check_unlock(), port_unlock, and TRUE.

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void _port_switch	(	Thread *	ntp,
		Thread *	otp
	)

Performs a context switch between two threads.

This is the most critical code in any port, this function is responsible for the context switch between 2 threads.

Note:: The implementation of this code affects directly the context switch performance so optimize here as much as you can.

Parameters:

[in]	ntp	the thread to be switched in
[in]	otp	the thread to be switched out

Definition at line 229 of file chcore_v7m.c.

void _port_thread_start ( void )

Start a thread by invoking its work function.

If the work function returns chThdExit() is automatically invoked.

Definition at line 252 of file chcore_v7m.c.

References chSysUnlock.

void port_halt ( void )

Halts the system.

Note:: The function is declared as a weak symbol, it is possible to redefine it in your application code.

Definition at line 39 of file chcore.c.

References port_disable, and TRUE.

Define Documentation

#define CORTEX_BASEPRI_DISABLED 0

Disabled value for BASEPRI register.

Definition at line 39 of file chcore_v7m.h.

#define PORT_IDLE_THREAD_STACK_SIZE 16

Stack size for the system idle thread.

This size depends on the idle thread implementation, usually the idle thread should take no more space than those reserved by PORT_INT_REQUIRED_STACK.

Note:: In this port it is set to 16 because the idle thread does have a stack frame when compiling without optimizations. You may reduce this value to zero when compiling with optimizations.

Definition at line 59 of file chcore_v7m.h.

#define PORT_INT_REQUIRED_STACK 32

Per-thread stack overhead for interrupts servicing.

This constant is used in the calculation of the correct working area size.

Note:: In this port this value is conservatively set to 32 because the function chSchDoReschedule() can have a stack frame, especially with compiler optimizations disabled. The value can be reduced when compiler optimizations are enabled.

Definition at line 72 of file chcore_v7m.h.

#define CORTEX_ENABLE_WFI_IDLE FALSE

Enables the use of the WFI instruction in the idle thread loop.

Definition at line 79 of file chcore_v7m.h.

#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)

SYSTICK handler priority.

Note:: The default SYSTICK handler priority is calculated as the priority level in the middle of the numeric priorities range.

Definition at line 88 of file chcore_v7m.h.

#define CORTEX_USE_FPU CORTEX_HAS_FPU

FPU support in context switch.

Activating this option activates the FPU support in the kernel.

Definition at line 99 of file chcore_v7m.h.

#define CORTEX_SIMPLIFIED_PRIORITY FALSE

Simplified priority handling flag.

Activating this option makes the Kernel work in compact mode.

Definition at line 111 of file chcore_v7m.h.

#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)

SVCALL handler priority.

Note:: The default SVCALL handler priority is defaulted to CORTEX_MAXIMUM_PRIORITY+1, this reserves the CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts priority level.

Definition at line 122 of file chcore_v7m.h.

Referenced by _port_init().

#define CORTEX_VTOR_INIT 0x00000000

NVIC VTOR initialization expression.

Definition at line 132 of file chcore_v7m.h.

Referenced by _port_init().

#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)

NVIC PRIGROUP initialization expression.

The default assigns all available priority bits as preemption priority with no sub-priority.

Definition at line 141 of file chcore_v7m.h.

Referenced by _port_init().

#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)

Maximum usable priority for normal ISRs.

Definition at line 152 of file chcore_v7m.h.

#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY)

BASEPRI level within kernel lock.

Note:: In compact kernel mode this constant value is enforced to zero.

Definition at line 158 of file chcore_v7m.h.

#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL

PendSV priority level.

Note:: This priority is enforced to be equal to CORTEX_BASEPRI_KERNEL, this handler always have the highest priority that cannot preempt the kernel.

Definition at line 172 of file chcore_v7m.h.

#define CH_ARCHITECTURE_ARM_v7M

Macro defining the specific ARM architecture.

Definition at line 182 of file chcore_v7m.h.

#define CH_ARCHITECTURE_NAME "ARMv7-M"

Name of the implemented architecture.

Definition at line 187 of file chcore_v7m.h.

#define CH_CORE_VARIANT_NAME "Cortex-M3"

Name of the architecture variant.

Definition at line 192 of file chcore_v7m.h.

#define CH_PORT_INFO "Advanced kernel mode"

Port-specific information string.

Definition at line 208 of file chcore_v7m.h.

#define SETUP_CONTEXT	(	workspace,
		wsize,
		pf,
		arg
	)

Value:

{                          \
  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
                                     wsize -                                \
                                     sizeof(struct intctx));                \
  tp->p_ctx.r13->r4 = (void *)(pf);                                         \
  tp->p_ctx.r13->r5 = (void *)(arg);                                        \
  tp->p_ctx.r13->lr = (void *)(_port_thread_start);                         \
}

Platform dependent part of the chThdCreateI() API.

This code usually setup the context switching frame represented by an intctx structure.

Definition at line 307 of file chcore_v7m.h.

#define STACK_ALIGN ( n ) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)

Enforces a correct alignment for a stack area size value.

Definition at line 319 of file chcore_v7m.h.

#define THD_WA_SIZE ( n )

Value:

STACK_ALIGN(sizeof(Thread) +                         \
                                   sizeof(struct intctx) +                  \
                                   sizeof(struct extctx) +                  \
                                   (n) + (PORT_INT_REQUIRED_STACK))

Computes the thread working area global size.

Definition at line 324 of file chcore_v7m.h.

#define WORKING_AREA	(	s,
		n
	)	stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]

Static working area allocation.

This macro is used to allocate a static thread working area aligned as both position and size.

Definition at line 334 of file chcore_v7m.h.

#define PORT_IRQ_PROLOGUE ( )

IRQ prologue code.

This macro must be inserted at the start of all IRQ handlers enabled to invoke system APIs.

Definition at line 341 of file chcore_v7m.h.

#define PORT_IRQ_EPILOGUE ( ) _port_irq_epilogue()

IRQ epilogue code.

This macro must be inserted at the end of all IRQ handlers enabled to invoke system APIs.

Definition at line 348 of file chcore_v7m.h.

#define PORT_IRQ_HANDLER ( id ) void id(void)

IRQ handler function declaration.

Note:: id can be a function name or a vector number depending on the port implementation.

Definition at line 355 of file chcore_v7m.h.

#define PORT_FAST_IRQ_HANDLER ( id ) void id(void)

Fast IRQ handler function declaration.

Note:: id can be a function name or a vector number depending on the port implementation.

Definition at line 362 of file chcore_v7m.h.

#define port_init ( ) _port_init()

Port-related initialization code.

Definition at line 367 of file chcore_v7m.h.

#define port_lock ( )

Value:

{                                                       \
  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;                 \
  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");            \
}

Kernel-lock action.

Usually this function just disables interrupts but may perform more actions.

Note:: In this port this it raises the base priority to kernel level.

Definition at line 377 of file chcore_v7m.h.

#define port_unlock ( )

Value:

{                                                     \
  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;               \
  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");            \
}

Kernel-unlock action.

Usually this function just enables interrupts but may perform more actions.

Note:: In this port this it lowers the base priority to user level.

Definition at line 398 of file chcore_v7m.h.

#define port_lock_from_isr ( ) port_lock()

Kernel-lock action from an interrupt handler.

This function is invoked before invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.

Note:: Same as port_lock() in this port.

Definition at line 418 of file chcore_v7m.h.

#define port_unlock_from_isr ( ) port_unlock()

Kernel-unlock action from an interrupt handler.

This function is invoked after invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.

Note:: Same as port_unlock() in this port.

Definition at line 427 of file chcore_v7m.h.

#define port_disable ( ) asm volatile ("cpsid i" : : : "memory")

Disables all the interrupt sources.

Note:: Of course non-maskable interrupt sources are not included.; In this port it disables all the interrupt sources by raising the priority mask to level 0.

Definition at line 435 of file chcore_v7m.h.

#define port_suspend ( )

Value:

{                                                    \
  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;                 \
  asm volatile ("msr     BASEPRI, %0                    \n\t"               \
                "cpsie   i" : : "r" (tmp) : "memory");                      \
}

Disables the interrupt sources below kernel-level priority.

Note:: Interrupt sources above kernel level remains enabled.; In this port it raises/lowers the base priority to kernel level.

Definition at line 443 of file chcore_v7m.h.

#define port_enable ( )

Value:

{                                                     \
  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;               \
  asm volatile ("msr     BASEPRI, %0                    \n\t"               \
                "cpsie   i" : : "r" (tmp) : "memory");                      \
}

Enables all the interrupt sources.

Note:: In this port it lowers the base priority to user level.

Definition at line 457 of file chcore_v7m.h.

#define port_wait_for_interrupt ( )

Value:

{                                         \
  asm volatile ("wfi" : : : "memory");                                      \
}

Enters an architecture-dependent IRQ-waiting mode.

The function is meant to return when an interrupt becomes pending. The simplest implementation is an empty function or macro but this would not take advantage of architecture-specific power saving modes.

Note:: Implemented as an inlined WFI instruction.

Definition at line 475 of file chcore_v7m.h.

#define port_switch	(	ntp,
		otp
	)	_port_switch(ntp, otp)

Performs a context switch between two threads.

This is the most critical code in any port, this function is responsible for the context switch between 2 threads.

Note:: The implementation of this code affects directly the context switch performance so optimize here as much as you can.

Parameters:

[in]	ntp	the thread to be switched in
[in]	otp	the thread to be switched out

Definition at line 493 of file chcore_v7m.h.

Typedef Documentation

typedef void* regarm_t

Generic ARM register.

Definition at line 222 of file chcore_v7m.h.

Detailed Description

Data Structures

Functions

Defines

Typedefs

Function Documentation

Define Documentation

Typedef Documentation