Collaboration diagram for ARM Cortex-Mx:

Detailed Description

ARM Cortex-Mx port for the IAR compiler.

Introduction

This port supports all the cores implementing the ARMv6-M and ARMv7-M architectures.

Kernel Modes

The Cortex-Mx port supports two distinct kernel modes:

Advanced Kernel mode. In this mode the kernel only masks interrupt sources with priorities below or equal to the CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by the kernel critical sections and can be used for fast interrupts. This mode is not available in the ARMv6-M architecture which does not support priority masking.
Compact Kernel mode. In this mode the kernel handles IRQ priorities in a simplified way, all interrupt sources are disabled when the kernel enters into a critical zone and re-enabled on exit. This is simple and adequate for most applications, this mode results in a more compact and faster kernel.

The selection of the mode is performed using the port configuration option CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of interrupts there are no other differences between the two modes. The kernel API is exactly the same.

System logical states in Compact Kernel mode

The ChibiOS/RT logical System States are mapped as follow in Compact Kernel mode:

Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated.
Normal. This is the state the system has after executing chSysInit(). In this state interrupts are enabled. The processor is running in thread-privileged mode.
Suspended. In this state the interrupt sources are globally disabled. The processor is running in thread-privileged mode. In this mode this state is not different from the Disabled state.
Disabled. In this state the interrupt sources are globally disabled. The processor is running in thread-privileged mode. In this mode this state is not different from the Suspended state.
Sleep. This state is entered with the execution of the specific instruction wfi.
S-Locked. In this state the interrupt sources are globally disabled. The processor is running in thread-privileged mode.
I-Locked. In this state the interrupt sources are globally disabled. The processor is running in exception-privileged mode.
Serving Regular Interrupt. In this state the interrupt sources are not globally masked but only interrupts with higher priority can preempt the current handler. The processor is running in exception-privileged mode.
Serving Fast Interrupt. Not implemented in compact kernel mode.
Serving Non-Maskable Interrupt. The Cortex-Mx has a specific asynchronous NMI vector and several synchronous fault vectors that can be considered belonging to this category.
Halted. Implemented as an infinite loop after globally masking all the maskable interrupt sources. The ARM state is whatever the processor was running when chSysHalt() was invoked.

System logical states in Advanced Kernel mode

The ChibiOS/RT logical System States are mapped as follow in the Advanced Kernel mode:

Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated.
Normal. This is the state the system has after executing chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register set at CORTEX_BASEPRI_USER level, interrupts are not masked. The processor is running in thread-privileged mode.
Suspended. In this state the interrupt sources are not globally masked but the BASEPRI register is set to CORTEX_BASEPRI_KERNEL thus masking any interrupt source with lower or equal priority. The processor is running in thread-privileged mode.
Disabled. Interrupt sources are globally masked. The processor is running in thread-privileged mode.
Sleep. This state is entered with the execution of the specific instruction wfi.
S-Locked. In this state the interrupt sources are not globally masked but the BASEPRI register is set to CORTEX_BASEPRI_KERNEL thus masking any interrupt source with lower or equal priority. The processor is running in thread-privileged mode.
I-Locked. In this state the interrupt sources are not globally masked but the BASEPRI register is set to CORTEX_BASEPRI_KERNEL thus masking any interrupt source with lower or equal priority. The processor is running in exception-privileged mode.
Serving Regular Interrupt. In this state the interrupt sources are not globally masked but only interrupts with higher priority can preempt the current handler. The processor is running in exception-privileged mode.
Serving Fast Interrupt. Fast interrupts are defined as interrupt sources having higher priority level than the kernel (CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to the I-Locked state because fast interrupts can preempt the kernel critical zone.
This state is not implemented in the ARMv6-M implementation because priority masking is not present in this architecture.
Serving Non-Maskable Interrupt. The Cortex-Mx has a specific asynchronous NMI vector and several synchronous fault vectors that can be considered belonging to this category.
Halted. Implemented as an infinite loop after globally masking all the maskable interrupt sources. The ARM state is whatever the processor was running when chSysHalt() was invoked.

ARM Cortex-Mx/IAR port notes

The ARM Cortex-Mx port is organized as follow:

The main() function is invoked in thread-privileged mode.
Each thread has a private process stack, the system has a single main stack where all the interrupts and exceptions are processed.
The threads are started in thread-privileged mode.
Interrupt nesting and the other advanced core/NVIC features are supported.
The Cortex-Mx port is perfectly generic, support for more devices can be easily added by adding a subdirectory under ./os/ports/IAR/ARMCMx and giving it the name of the new device, then copy the files from another device into the new directory and customize them for the new device.