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ChibiOS/RT
2.5.1 |
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ARMv7-M specific port code, structures and macros.
Data Structures | |
| struct | context |
Platform dependent part of the Thread structure. More... | |
Functions | |
| CH_IRQ_HANDLER (SysTickVector) | |
| System Timer vector. | |
| void | SVCallVector (void) |
| SVC vector. | |
| void | PendSVVector (void) |
| PendSV vector. | |
| void | _port_init (void) |
| Port-related initialization code. | |
| void | _port_irq_epilogue (void) |
| Exception exit redirection to _port_switch_from_isr(). | |
| void | port_halt (void) |
| Halts the system. | |
Defines | |
| #define | CORTEX_BASEPRI_DISABLED 0 |
| Disabled value for BASEPRI register. | |
| #define | PORT_IDLE_THREAD_STACK_SIZE 16 |
| Stack size for the system idle thread. | |
| #define | PORT_INT_REQUIRED_STACK 32 |
| Per-thread stack overhead for interrupts servicing. | |
| #define | CORTEX_ENABLE_WFI_IDLE FALSE |
| Enables the use of the WFI instruction in the idle thread loop. | |
| #define | CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) |
| SYSTICK handler priority. | |
| #define | CORTEX_USE_FPU CORTEX_HAS_FPU |
| FPU support in context switch. | |
| #define | CORTEX_SIMPLIFIED_PRIORITY FALSE |
| Simplified priority handling flag. | |
| #define | CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) |
| SVCALL handler priority. | |
| #define | CORTEX_VTOR_INIT 0x00000000 |
| NVIC VTOR initialization expression. | |
| #define | CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) |
| NVIC PRIGROUP initialization expression. | |
| #define | CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) |
| Maximum usable priority for normal ISRs. | |
| #define | CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) |
| BASEPRI level within kernel lock. | |
| #define | CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL |
| PendSV priority level. | |
| #define | CH_ARCHITECTURE_ARM_v7M |
| Macro defining the specific ARM architecture. | |
| #define | CH_ARCHITECTURE_NAME "ARMv7-M" |
| Name of the implemented architecture. | |
| #define | CH_CORE_VARIANT_NAME "Cortex-M3" |
| Name of the architecture variant. | |
| #define | CH_PORT_INFO "Advanced kernel mode" |
| Port-specific information string. | |
| #define | SETUP_CONTEXT(workspace, wsize, pf, arg) |
Platform dependent part of the chThdCreateI() API. | |
| #define | STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) |
| Enforces a correct alignment for a stack area size value. | |
| #define | THD_WA_SIZE(n) |
| Computes the thread working area global size. | |
| #define | WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] |
| Static working area allocation. | |
| #define | PORT_IRQ_PROLOGUE() |
| IRQ prologue code. | |
| #define | PORT_IRQ_EPILOGUE() _port_irq_epilogue() |
| IRQ epilogue code. | |
| #define | PORT_IRQ_HANDLER(id) void id(void) |
| IRQ handler function declaration. | |
| #define | PORT_FAST_IRQ_HANDLER(id) void id(void) |
| Fast IRQ handler function declaration. | |
| #define | port_init() _port_init() |
| Port-related initialization code. | |
| #define | port_lock() __set_BASEPRI(CORTEX_BASEPRI_KERNEL) |
| Kernel-lock action. | |
| #define | port_unlock() __set_BASEPRI(CORTEX_BASEPRI_DISABLED) |
| Kernel-unlock action. | |
| #define | port_lock_from_isr() port_lock() |
| Kernel-lock action from an interrupt handler. | |
| #define | port_unlock_from_isr() port_unlock() |
| Kernel-unlock action from an interrupt handler. | |
| #define | port_disable() __disable_interrupt() |
| Disables all the interrupt sources. | |
| #define | port_suspend() |
| Disables the interrupt sources below kernel-level priority. | |
| #define | port_enable() |
| Enables all the interrupt sources. | |
| #define | port_wait_for_interrupt() asm ("wfi") |
| Enters an architecture-dependent IRQ-waiting mode. | |
| #define | port_switch(ntp, otp) _port_switch(ntp, otp) |
| Performs a context switch between two threads. | |
Typedefs | |
| typedef void * | regarm_t |
| Generic ARM register. | |
| typedef uint64_t | stkalign_t |
| Stack and memory alignment enforcement. | |
| CH_IRQ_HANDLER | ( | SysTickVector | ) |
System Timer vector.
This interrupt is used as system tick.
Definition at line 40 of file chcore_v7m.c.
References CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, chSysLockFromIsr, chSysTimerHandlerI(), and chSysUnlockFromIsr.

| void SVCallVector | ( | void | ) |
SVC vector.
The SVC vector is used for exception mode re-entering after a context switch.
Definition at line 58 of file chcore_v7m.c.
References port_unlock_from_isr.
| void PendSVVector | ( | void | ) |
PendSV vector.
The PendSV vector is used for exception mode re-entering after a context switch.
Definition at line 85 of file chcore_v7m.c.
| void _port_init | ( | void | ) |
Port-related initialization code.
Definition at line 111 of file chcore_v7m.c.
References CORTEX_PRIGROUP_INIT, CORTEX_PRIORITY_MASK, CORTEX_PRIORITY_PENDSV, CORTEX_PRIORITY_SVCALL, CORTEX_PRIORITY_SYSTICK, CORTEX_VTOR_INIT, HANDLER_PENDSV, HANDLER_SVCALL, HANDLER_SYSTICK, and nvicSetSystemHandlerPriority().

| void _port_irq_epilogue | ( | void | ) |
Exception exit redirection to _port_switch_from_isr().
Definition at line 146 of file chcore_v7m.c.
References chSchIsPreemptionRequired(), port_lock_from_isr, and port_unlock_from_isr.

| void port_halt | ( | void | ) |
Halts the system.
Definition at line 39 of file chcore.c.
References port_disable, and TRUE.
| #define CORTEX_BASEPRI_DISABLED 0 |
Disabled value for BASEPRI register.
Definition at line 39 of file chcore_v7m.h.
| #define PORT_IDLE_THREAD_STACK_SIZE 16 |
Stack size for the system idle thread.
This size depends on the idle thread implementation, usually the idle thread should take no more space than those reserved by PORT_INT_REQUIRED_STACK.
Definition at line 59 of file chcore_v7m.h.
| #define PORT_INT_REQUIRED_STACK 32 |
Per-thread stack overhead for interrupts servicing.
This constant is used in the calculation of the correct working area size.
chSchDoReschedule() can have a stack frame, especially with compiler optimizations disabled. The value can be reduced when compiler optimizations are enabled. Definition at line 72 of file chcore_v7m.h.
| #define CORTEX_ENABLE_WFI_IDLE FALSE |
Enables the use of the WFI instruction in the idle thread loop.
Definition at line 79 of file chcore_v7m.h.
| #define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) |
SYSTICK handler priority.
Definition at line 88 of file chcore_v7m.h.
| #define CORTEX_USE_FPU CORTEX_HAS_FPU |
FPU support in context switch.
Activating this option activates the FPU support in the kernel.
Definition at line 99 of file chcore_v7m.h.
| #define CORTEX_SIMPLIFIED_PRIORITY FALSE |
Simplified priority handling flag.
Activating this option makes the Kernel work in compact mode.
Definition at line 111 of file chcore_v7m.h.
| #define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) |
SVCALL handler priority.
CORTEX_MAXIMUM_PRIORITY+1, this reserves the CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts priority level. Definition at line 122 of file chcore_v7m.h.
Referenced by _port_init().
| #define CORTEX_VTOR_INIT 0x00000000 |
NVIC VTOR initialization expression.
Definition at line 132 of file chcore_v7m.h.
Referenced by _port_init().
| #define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) |
NVIC PRIGROUP initialization expression.
The default assigns all available priority bits as preemption priority with no sub-priority.
Definition at line 141 of file chcore_v7m.h.
Referenced by _port_init().
| #define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) |
Maximum usable priority for normal ISRs.
Definition at line 152 of file chcore_v7m.h.
| #define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) |
BASEPRI level within kernel lock.
Definition at line 158 of file chcore_v7m.h.
| #define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL |
PendSV priority level.
CORTEX_BASEPRI_KERNEL, this handler always have the highest priority that cannot preempt the kernel. Definition at line 172 of file chcore_v7m.h.
| #define CH_ARCHITECTURE_ARM_v7M |
Macro defining the specific ARM architecture.
Definition at line 182 of file chcore_v7m.h.
| #define CH_ARCHITECTURE_NAME "ARMv7-M" |
Name of the implemented architecture.
Definition at line 187 of file chcore_v7m.h.
| #define CH_CORE_VARIANT_NAME "Cortex-M3" |
Name of the architecture variant.
Definition at line 192 of file chcore_v7m.h.
| #define CH_PORT_INFO "Advanced kernel mode" |
Port-specific information string.
Definition at line 208 of file chcore_v7m.h.
| #define SETUP_CONTEXT | ( | workspace, | |
| wsize, | |||
| pf, | |||
| arg | |||
| ) |
{ \
tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
wsize - \
sizeof(struct intctx)); \
tp->p_ctx.r13->r4 = (regarm_t)pf; \
tp->p_ctx.r13->r5 = (regarm_t)arg; \
tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \
}
Platform dependent part of the chThdCreateI() API.
This code usually setup the context switching frame represented by an intctx structure.
Definition at line 313 of file chcore_v7m.h.
| #define STACK_ALIGN | ( | n | ) | ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) |
Enforces a correct alignment for a stack area size value.
Definition at line 325 of file chcore_v7m.h.
| #define THD_WA_SIZE | ( | n | ) |
STACK_ALIGN(sizeof(Thread) + \ sizeof(struct intctx) + \ sizeof(struct extctx) + \ (n) + (PORT_INT_REQUIRED_STACK))
Computes the thread working area global size.
Definition at line 330 of file chcore_v7m.h.
| #define WORKING_AREA | ( | s, | |
| n | |||
| ) | stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] |
Static working area allocation.
This macro is used to allocate a static thread working area aligned as both position and size.
Definition at line 340 of file chcore_v7m.h.
| #define PORT_IRQ_PROLOGUE | ( | ) |
IRQ prologue code.
This macro must be inserted at the start of all IRQ handlers enabled to invoke system APIs.
Definition at line 347 of file chcore_v7m.h.
| #define PORT_IRQ_EPILOGUE | ( | ) | _port_irq_epilogue() |
IRQ epilogue code.
This macro must be inserted at the end of all IRQ handlers enabled to invoke system APIs.
Definition at line 354 of file chcore_v7m.h.
| #define PORT_IRQ_HANDLER | ( | id | ) | void id(void) |
IRQ handler function declaration.
id can be a function name or a vector number depending on the port implementation. Definition at line 361 of file chcore_v7m.h.
| #define PORT_FAST_IRQ_HANDLER | ( | id | ) | void id(void) |
Fast IRQ handler function declaration.
id can be a function name or a vector number depending on the port implementation. Definition at line 368 of file chcore_v7m.h.
| #define port_init | ( | ) | _port_init() |
Port-related initialization code.
Definition at line 373 of file chcore_v7m.h.
| #define port_lock | ( | ) | __set_BASEPRI(CORTEX_BASEPRI_KERNEL) |
Kernel-lock action.
Usually this function just disables interrupts but may perform more actions.
Definition at line 382 of file chcore_v7m.h.
| #define port_unlock | ( | ) | __set_BASEPRI(CORTEX_BASEPRI_DISABLED) |
Kernel-unlock action.
Usually this function just enables interrupts but may perform more actions.
Definition at line 394 of file chcore_v7m.h.
| #define port_lock_from_isr | ( | ) | port_lock() |
Kernel-lock action from an interrupt handler.
This function is invoked before invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.
port_lock() in this port. Definition at line 406 of file chcore_v7m.h.
| #define port_unlock_from_isr | ( | ) | port_unlock() |
Kernel-unlock action from an interrupt handler.
This function is invoked after invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.
port_unlock() in this port. Definition at line 415 of file chcore_v7m.h.
| #define port_disable | ( | ) | __disable_interrupt() |
Disables all the interrupt sources.
Definition at line 423 of file chcore_v7m.h.
| #define port_suspend | ( | ) |
{ \
__set_BASEPRI(CORTEX_BASEPRI_KERNEL); \
__enable_interrupt(); \
}
Disables the interrupt sources below kernel-level priority.
Definition at line 431 of file chcore_v7m.h.
| #define port_enable | ( | ) |
{ \
__set_BASEPRI(CORTEX_BASEPRI_DISABLED); \
__enable_interrupt(); \
}
Enables all the interrupt sources.
Definition at line 444 of file chcore_v7m.h.
| #define port_wait_for_interrupt | ( | ) | asm ("wfi") |
Enters an architecture-dependent IRQ-waiting mode.
The function is meant to return when an interrupt becomes pending. The simplest implementation is an empty function or macro but this would not take advantage of architecture-specific power saving modes.
WFI instruction. Definition at line 461 of file chcore_v7m.h.
| #define port_switch | ( | ntp, | |
| otp | |||
| ) | _port_switch(ntp, otp) |
Performs a context switch between two threads.
This is the most critical code in any port, this function is responsible for the context switch between 2 threads.
| [in] | ntp | the thread to be switched in |
| [in] | otp | the thread to be switched out |
Definition at line 477 of file chcore_v7m.h.
| typedef void* regarm_t |
Generic ARM register.
Definition at line 222 of file chcore_v7m.h.
| typedef uint64_t stkalign_t |
Stack and memory alignment enforcement.
Definition at line 230 of file chcore_v7m.h.