Collaboration diagram for Core Port Implementation:

Detailed Description

ARM Cortex-Mx specific port code, structures and macros.

Data Structures
struct	extctx
	Interrupt saved context. More...
struct	intctx
	System saved context. More...
Modules
	ARMv6-M Specific Implementation
	ARMv7-M Specific Implementation
Functions
void	port_halt (void)
	Halts the system.
Defines
#define	CORTEX_M0 0
	Cortex-M0 variant.
#define	CORTEX_M1 1
	Cortex-M1 variant.
#define	CORTEX_M3 3
	Cortex-M3 variant.
#define	CORTEX_M4 4
	Cortex-M4 variant.
#define	CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
	Total priority levels.
#define	CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
	Minimum priority level.
#define	CORTEX_MAXIMUM_PRIORITY 0
	Maximum priority level.
#define	CORTEX_IS_VALID_PRIORITY(n) (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
	Priority level verification macro.
#define	CORTEX_IS_VALID_KERNEL_PRIORITY(n) (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
	Priority level verification macro.
#define	CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
	Priority level to priority mask conversion macro.
#define	CH_ARCHITECTURE_ARM
	Macro defining a generic ARM architecture.
#define	CH_COMPILER_NAME "IAR"
	Name of the compiler supported by this port.
#define	PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
	Excludes the default `chSchIsPreemptionRequired()implementation`.
#define	chSchIsPreemptionRequired()
	Inline-able version of this kernel function.
#define	INLINE inline
	Inline function modifier.
#define	ROMCONST const
	ROM constant modifier.
#define	PACK_STRUCT_STRUCT
	Packed structure modifier (within).
#define	PACK_STRUCT_BEGIN __packed
	Packed structure modifier (before).
#define	PACK_STRUCT_END
	Packed structure modifier (after).
Typedefs
typedef uint64_t	stkalign_t
	Stack and memory alignment enforcement.
typedef int32_t	bool_t
typedef uint8_t	tmode_t
typedef uint8_t	tstate_t
typedef uint8_t	trefs_t
typedef uint8_t	tslices_t
typedef uint32_t	tprio_t
typedef int32_t	msg_t
typedef int32_t	eventid_t
typedef uint32_t	eventmask_t
typedef uint32_t	flagsmask_t
typedef uint32_t	systime_t
typedef int32_t	cnt_t

Function Documentation

void port_halt ( void )

Halts the system.

Note:: The function is declared as a weak symbol, it is possible to redefine it in your application code.

Definition at line 39 of file ports/IAR/ARMCMx/chcore.c.

References port_disable, and TRUE.

Define Documentation

#define CORTEX_M0 0

Cortex-M0 variant.

Definition at line 44 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_M1 1

Cortex-M1 variant.

Definition at line 45 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_M3 3

Cortex-M3 variant.

Definition at line 46 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_M4 4

Cortex-M4 variant.

Definition at line 47 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)

Total priority levels.

Definition at line 64 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)

Minimum priority level.

This minimum priority level is calculated from the number of priority bits supported by the specific Cortex-Mx implementation.

Definition at line 71 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_MAXIMUM_PRIORITY 0

Maximum priority level.

The maximum allowed priority level is always zero.

Definition at line 77 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_IS_VALID_PRIORITY ( n ) (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))

Priority level verification macro.

Definition at line 86 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_IS_VALID_KERNEL_PRIORITY ( n ) (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))

Priority level verification macro.

Definition at line 92 of file ports/IAR/ARMCMx/chcore.h.

#define CORTEX_PRIORITY_MASK ( n ) ((n) << (8 - CORTEX_PRIORITY_BITS))

Priority level to priority mask conversion macro.

Definition at line 98 of file ports/IAR/ARMCMx/chcore.h.

#define CH_ARCHITECTURE_ARM

Macro defining a generic ARM architecture.

Definition at line 116 of file ports/IAR/ARMCMx/chcore.h.

#define CH_COMPILER_NAME "IAR"

Name of the compiler supported by this port.

Definition at line 121 of file ports/IAR/ARMCMx/chcore.h.

#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED

Excludes the default chSchIsPreemptionRequired()implementation.

Definition at line 171 of file ports/IAR/ARMCMx/chcore.h.

#define chSchIsPreemptionRequired ( void )

Value:

(currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio :           \
                      firstprio(&rlist.r_queue) >= currp->p_prio)

Inline-able version of this kernel function.

Definition at line 177 of file ports/IAR/ARMCMx/chcore.h.

#define INLINE inline

Inline function modifier.

Definition at line 55 of file ports/IAR/ARMCMx/chtypes.h.

#define ROMCONST const

ROM constant modifier.

Note:: It is set to use the "const" keyword in this port.

Definition at line 61 of file ports/IAR/ARMCMx/chtypes.h.

#define PACK_STRUCT_STRUCT

Packed structure modifier (within).

Note:: Empty in this port.

Definition at line 67 of file ports/IAR/ARMCMx/chtypes.h.

#define PACK_STRUCT_BEGIN __packed

Packed structure modifier (before).

Definition at line 72 of file ports/IAR/ARMCMx/chtypes.h.

#define PACK_STRUCT_END

Packed structure modifier (after).

Note:: Empty in this port.

Definition at line 78 of file ports/IAR/ARMCMx/chtypes.h.

Typedef Documentation

typedef uint64_t stkalign_t

Stack and memory alignment enforcement.

Note:: In this architecture the stack alignment is enforced to 64 bits, 32 bits alignment is supported by hardware but deprecated by ARM, the implementation choice is to not offer the option.

Definition at line 149 of file ports/IAR/ARMCMx/chcore.h.

typedef int32_t bool_t

Fast boolean type.

Definition at line 39 of file ports/IAR/ARMCMx/chtypes.h.

typedef uint8_t tmode_t

Thread flags.

Definition at line 40 of file ports/IAR/ARMCMx/chtypes.h.

typedef uint8_t tstate_t

Thread state.

Definition at line 41 of file ports/IAR/ARMCMx/chtypes.h.

typedef uint8_t trefs_t

Thread references counter.